`timescale 1ns / 100ps

module ProgramCounter_tb;

	reg clk;
	reg reset;
	reg load;
	reg inc;
	reg Mode;
	reg [7:0] ResetVal;
	reg [7:0] LoadVal;

	wire [7:0] PCoutput;

	ProgramCounter dut (
		.clk(clk),
		.ResetVal(ResetVal),
		.LoadVal(LoadVal),
		.reset(reset),
		.load(load),
		.inc(inc),
		.Mode(Mode),
		.PCoutput(PCoutput)
	);

	always #10 clk = ~clk;

	initial begin
		clk = 0;
		reset = 0;
		load = 0;
		inc = 0;
		Mode = 0;
		ResetVal = 8'd05;
		LoadVal = 8'd0;

		#20;
		reset = 1;
		#20;
		reset = 0;

		#20;
		inc = 1;
		LoadVal = 8'd200;
		load = 1;
		#20;
		load = 0;

		#2000;
		Mode = 1;
		#200;
		inc = 1;
		#200;
		inc = 0;

		#20;
		ResetVal = 8'd99;
		reset = 1;
		load  = 1;
		#20;
		reset = 0;
		load  = 0;

		#20;
		inc = 1;
		#500;
		inc = 0;

		#20;
		$stop;
	end

endmodule
